Sept. 19, 2005 -- Payam Heydari, Assistant Professor in the Department of Electrical Engineering and Computer Science, and a Calit2 academic participant is the recipient of a National Science Foundation (NSF) grant that supports his research on a new analytical study that enables circuit designers to efficiently analyze and design ultra-high-speed on-chip interconnects, which are used to deliver high frequency signals across the chip. This study takes into account the statistical variations of interconnects due to manufacturing process variations.
The research, funded with a $100,000 NSF grant, will have tremendous impact on the next generations of interconnect-dominated system-on-chips (SoCs) fabricated in nanometer complementary metal oxide semiconductor (CMOS) technologies, in which process variations will have a dominating effect on their performance and reliability.
The grant will be used to develop new analytical theory and implement test chips to efficiently analyze high speed on-chip interconnects whose geometrical parameters are subject to statistical variations.
“The underlying idea of this research is to analyze the effect of process variations on high-speed interconnects both theoretically using efficient order-reduction techniques, and experimentally by testing the chips that will be designed in Broadband IC Lab at UC Irvine,” said Heydari.
Other research that is currently in progress in the Broadband IC Lab includes design of radio-frequency (RF) and analog ICs for next generation wireless/wireline communication transceivers.