Nader Bagherzadeh

Education: 

B.S., University of Texas,Austin, Electrical Engineering, 1977
M.S., University of Texas,Austin, Electrical Engineering, 1979
Ph.D., University of Texas,Austin, Computer Engineering, 1987

Address: 

The Henry Samueli School of Engineering
University of California, Irvine
Irvine, CA 92697-2625

ZOT Code: 
2625
Location: 
Office: EH 4209
Lab: EH 4120
Phone: 
(949) 824-2481 Lab
(949) 824-8720 Office
Fax: 
(949) 824-3203
Email: 
nader@uci.edu
Research: 

His current research area is involved with the design of next generation System-on-Chip (SoC) based on the notion of Network-on-Chip (NoC) architecture for connecting 100's of cores on the same die. He has worked on low power routers, wired and wireless on-chip communication, mapping and scheduling algorithms, as well as the fault-tolerance aspects of the NoC architectures.

An extension of his work is to apply the NoC architectural concept for the design of 3D ICs where the communication among cores are not limited to the 2D substrate, and Through-Silicon Via (TSV) as well as wireless communication are utilized for a flexible and scalable design.

Profile: 

Dr. Bagherzadeh is interested in hardware, software, and VLSI design of low-power and high performance computer systems for applications in mobile systems, computer graphics processing, 3D integrated circuits, memory structures, and integrated sensors.
 

Research topics: 
Parallel processing; Computer architecture