Chin Lee

Education: 

B.S., National Chiao-Tung University, Electrical Engineering, 1970
M.S., National Chiao-Tung University, Electrical Engineering, 1973
Ph.D., Carnegie Mellon University, Electrical Engineering, 1979

Address: 

The Henry Samueli School of Engineering
University of California, Irvine
Irvine, CA 92697-2625

ZOT Code: 
2625
Location: 
Office: EG 2226
Lab: EG 3324
Phone: 
(949) 824-4833 Lab
(949) 824-7462 Office
Fax: 
(949) 824-3732
Email: 
cclee@uci.edu
Research: 

(A) Aluminum Circuit Board (ACB) Technology
For a century, aluminum (Al) and its alloys have been excluded entirely from being adapted as boards or substrates of electronic circuits. While Al alloys have been used in airplane structures and automobile engine blocks, they were excused from electronics except in equipment casings and heatsinks. Al possesses superior physical properties: (1) lightweight, only 30% of Cu, the lightest among non-alkaline metals, (3) high electrical and thermal conductivities, (3) corrosion resistant, and (4) ease to manufacture. Why was not Al used as circuit boards or base plates? I set out to investigate Al in electronic applications. People did try to embrace Al for electronic packaging but eventually gave up and forgot about it. Here are the reasons that I identified: (a) Unlike its friend Cu, Al is not solderable, (b) Al has high coefficient of thermal expansion (CTE), probably highest among metals, (c) Insulating layer cannot be reliably grown on Al. Just the high CTE alone has turned most people away. So, I began my ACB technology journey. We first developed a process to bond tin (Sn) to Al substrates, without flux, of course. We then bonded large Si chips to Al substrates using fluxless Sn. The bonded structures survived the terrible CTE mismatch between Si and Al, the largest in electronic packaging. We then invented a process to grow high quality oxide layer on Al substrates, and further found a process to place high quality Cu film, up to 25µm, over the oxide. As you can see, all the hurdles or excuses of not choosing Al for circuit boards are eliminated. It is up to the electronic industry to reconsider its new role.

(B) Fluxless Soldering and Bonding Processes
Bonding means connecting two objects together in atomic scale on the interface. Soldering is a bonding process using solders. Solders are metallic alloys having low melting temperature, 100-300°C. At present, the most popular solder is alloy of tin (Sn) with 3 wt. % of silver (Ag) and 0.5 wt. % of Cu. It melts at 220°C. Flux contains organic acidic resin as main ingredient.It is used in every industrial soldering operation to reduce and remove oxides on the solder and on the metal to be soldered to, such as Cu. Without flux, solder will not bond to the metal. Flux and residues are easily trapped in the solder joint, weakening the joint and increasing its fatigue. The electronic industry has been struggling with this problem and cannot see the light at the end of the tunnel. Well, for 2 decades, we have provided the light for the industry to see. Specifically, we have developed numerous fluxless processes to demonstrate void-free joints including: bonding gallium arsenide (GaAs) chip using gold-tin (Au-Sn) eutectic, bonding large silicon chips using Au-Sn alloy, bonding GaAs chips using multiple layers of Au and Sn deposited on chip backside, bonding GaAs chips on Cu substrates using multilayer In-Au composite. We also bonded Si to glass, Si to alumina (Al2O3 ceramic), Si to Cu, Si to molybdenum (Mo), and glass to alumina using Sn or Au-Sn. A new fluxless process using Cr/In/Au composite was invented. It needs a process temperature of only 200°C, but the resulting joint achieves 460°C melting temperature. High temperature joints, i.e., up to 850°C, were also fabricated using Ag-In, Ag-Sn, Cu-In and Cu-Sn systems at low process temperatures. In a specific design, the joint was converted entirely into solid solution phase (Ag) that has melting temperature higher than 850°C while the joint was made at 180°C. How could that be possible? Well, it is indeed possible. The systems that we have explored include: Au-Sn, Au-In, Ag-Sn, Ag-In, Cu-Sn, Cu-In, Sn-Bi and Sn-In for a wide variety of applications. We never used flux in any of our processes. Our most recent project is fluxless Sn bonding process without intermetallic compound (IMC) formation.

(C) Solid-state Atomic Bonding Technology

Solid-state bonding means bonding without molten phase. Why solid-state bonding? Well, it can be done at a temperature much lower than the melting temperature of the materials to be bonded. Why is low bonding temperature important? Here are reasons: most devices and materials cannot take high temperature, and high bonding temperature induces high stress on bonded structures due to CTE mismatch. Atomic bonding means bonding on atomic scale. Putting them together, solid-state atomic bonding means bonding in atomic scale without molten phase. Here is my theory: when A atoms and B atoms are brought within atomic range so that they see each other, bonding will occur provided that A atoms and B atoms are attracted to each other by sharing electrons. We had bonded silver foils to Cu substrates at 250°C with only 1,000psi of static pressure applied. This is less than 1/10 of pressure used in conventional thermal compression bonding. We had also bonded Si chips to Cu substrates using either Ag foils or electroplated Ag. Ag was chosen because of its superior physical properties: have highest electrical conductivity and thermal conductivity among metals, are ductile, and are highly reliable under thermal cycling environment. By using Au as the bonding medium in the solid-state bonding process, the pressure can be reduced to 160psi.

(D) Silver and Ag/Au Flip-chip Interconnect Technology

In flip-chip interconnect configuration, the Si chip is flipped with active surface facing down and connected to the package substrate using numerous small lead-free (Pb-free) solder joints. Compared to wire bonding, the flip-chip method provides two advantages: (1) very short connect length, thus low inductance and high operating frequency and (b) high input/output (I/O) connect density. At present, nearly all large scale integrated (LSI) circuit chips are connected by flip-chip method using solders. As transistor size on IC chips continues to scale down, the flip-chip joints have to shrink too. When the pitch (periodicity) of joints goes down to 100µm, shear strain and IMC issues on solder joints cannot be fundamentally overcome. The electronic industry has been struggling with this and could not find a way out. We turned to using pure Ag as the joint material. We have demonstrated Ag flip-chip joints with pitch of 40µm and size of 15µm between Si chips and Cu substrates. We have also demonstrated Cu/Ag, Cu/Au, and Ag/Cu composite flip-chip joints. Compared to solder-based flip-chip interconnect, Ag and Ag/Au flip-chip technology has 13 potential undisputable advantages:

a.    Higher electrical conductivity, 7.7 times of that of Pb-free solder,
b.    Higher thermal conductivity, 5.2 times of that of Pb-free solders,
c.     Completely fluxless; thus 100% green,
d.    No IMCs, all reliability issues associated with IMC and IMC growth do not exist,
e.     Ductile Ag can manage CTE mismatch between chips and packages,
f.     High melting temperature, 961ºC for Ag joints,
g.     No molten phase involved; the bump can better keep its shape and geometry,
h.    No molten phase involved; bridging of adjacent bumps less likely to occur,
i.      Aspect ratio of joints can be greater than 1,
j.      No under-fill material between chip and substrate is needed,
k.    No solder mask is needed,
l.      Higher alignment tolerance because of solid-state bonding,
m.   The size of the bumps is only limited by the photolithographic process.

(E)  Topology Microwave Filters on Coplanar Strip (CPS) Lines
The band-pass filer is made in a short section of a CPS line. It connects directly to input and output CPS lines without any transition. In this filter section, a topology on the CPS electrodes is carved to emulate a lumped-element RLC   circuit that gives the filer response. The topology filer does not cost any thing extra to fabricate; it is practically free.

Profile: 

Fellow, Institute of Electrical and Electronics Engineers
ISI (Institute of Scientific Information) highly cited researcher in engineering category

Research topics: 
Electronic Packaging, Fluxless Bonding Technology, Thermal Analysis and Measurement of Electronic Devices, Microwave Devices, Optics and Integrated Optics, Acoustics
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