Chin Lee

Chin Lee's picture

Chin Lee

Education:

B.S., National Chiao-Tung University, Electrical Engineering, 1970
M.S., National Chiao-Tung University, Electrical Engineering, 1973
Ph.D., Carnegie Mellon University, Electrical Engineering, 1979

Location:

The Henry Samueli School of Engineering
University of California, Irvine
Irvine, CA  92697-2625
zotcode: 2625

Room:

Office: EG 2226
Lab: EG 3324

Phone:

  • (949) 824-4833 Lab
  • (949) 824-7462 Office
  • (949) 824-3732 Fax

Research:

Fluxless Oxidation-Free Bonding Technology:

The objective is to invent and develop new bonding technology for electronic and photonic devices and packages. Numerous fluxless processes have been formulated to produce nearly void-free joints including: bonding gallium arsenide (GaAs) dice using gold-tin eutectic alloy, bonding large silicon dice using gold-tin alloy, bonding GaAs dice using multiple layers of gold and tin deposited on the back side of the wafer without using gold tin preforms, bonding GaAs dice on copper substrates using multilayer indium-gold composite. We also bonded Si to glass, Si to alumina, Si to Cu, Si to Mo, and glass to alumina. Recently, a new fluxless process was developed using Cr/In/Au multilayer composite. This process requires a process temperature of only 200 degrees C but the resulting joint has a re-melting temperature of 460 degrees C. Very high temperature joints, i.e., up to 700 degrees C, were also fabricated using Ag-In, Ag-Sn, Cu-In and Cu-Sn alloys at low process temperatures. In one specific design, the joint was converted entirely into solid solution phase (Ag) that has a melting temperature higher than 850 degrees C. Other systems explored for fluxless bonding include Sn-Pb, Sn-In, Sn-Cu, Sn-Ag, In-Cu, and In-Ag for a wide variety of applications. Scanning acoustic microscopy (SAM) is used to examine the bonding quality and scanning election microscopy with EDX is used to study the composition and grain distribution and microstructure of the joints. All the processes developed are entirely fluxless, i.e., no flux needed during bonding.

Direct Bonding Technology:

Silver foils were bonded directly to Cu substrates with only 1000psi of static pressure applied. The bonding process was performed at low temperature of 250 degrees C in 100millitorr vacuum.  This is direct solid-state bonding between Ag and Cu. There is no molten phase. The structure of Cu substrate laminated with Ag foil can replace a Cu substrate to achieve better electrical, thermal, and mechanical performances in device packaging. Ag has higher electrical conductivity and thermal conductivity that Cu. Its yield strength is much lower than Cu and thus can incur shear plastic strain at much lower stress to accommodate displacement difference between a semiconductor chip and the substrate due to CTE mismatch.  Recently we succeeded in bonding a Si chip to a Cu substrate using pure Ag layer without any molten phase.

Ag-based Flip Chip Technology:

In flip-chip packaging, the Si chips are flipped with active surface facing down and connected to the package by many small lead-free (Pb-free) solder joints. In our new design, Ag-rich material is used to make the interconnect joints or columns. Each interconnect column consists of pure Ag as the base with a section of (Ag) which is the solid solution of indium in Ag. Comparing to Pb-free solders, Ag has much higher electrical conductivity, much higher thermal conductivity, and lower yield strength. The columns can also be made smaller because the molten phase is confined during the bonding process. Consequently, the resulting packages will provide better electrical performance, better thermal performance, more I/O pins per cm, and lower shear stress.  The success of this technology will have revolution impact on electronic products.

Topology Microwave Filters on Coplanar Strip (CPS) Lines:

The filer is a short section of CPS electrodes in a CPS line. It connects automatically to the input and output CPS lines without any transition section. In this electrode section, a topology on the electrodes is carved to emulate a lumped-element RL circuit that gives the filer response. The topology filer does not cost any thing extra to fabricate.

Electrical and Thermal Studies of AlGaN/GaN Heterojunction Field-effect Transistors and InGaN/GaN Light Emitting devices.

Biography:

Fellow, Institute of Electrical and Electronics Engineers