Frame Buffer (FB)

M1:

This group is working on interfaces between TinyRISC, DMAC and RC array. The MorphoSys FB is a fast memory buffer capable of running synchronously at 100MHz.The core memory array is made up of SRAM cells and data is directed using multiplexers and buffers. The FB interfaces directly with the RC, DMAC and TinyRISC processor. It functions as a buffer for SDRAM data between the DMAC and RC. There are two separate memory buffers called sets that are internal to the FB. Each set comprises of a pair of banks. The DMAC accesses one bank at a time. An RC accesses two banks when it is reading.


M1 FB Structure

Newest Version of MorphoSys:

FB core consists of 64 memory banks; each bank corresponds to an RC in RC Array, and can transfer 16 bit words of data to its corresponding RC. FB has gone through a series of modifications that gives it more flexibility and makes it faster. One of this architecture's latest modifications is the two addressing modes which allow for a fast and continuous data movement within the system.

The first figure shows the FB Interface, the second figure shows both a memory array row in FB and the FB reconfigurable bus.

Contact us at:
  • Phone: (949) 824-5689
  • Fax: (949) 824-3779
  • Postal address:
    University of California, Irvine
    Department of Electrical Engineering and Computer Science
    Irvine, CA 92697-2625
  • General Info: MorphoSys@uci.edu

References:


MorphoSys V3.0
Last Updated: 09/01/2003
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