Publication
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh, "Parallel FFT Algorithms on Network-on-Chips," 5th International Conference on Information Technology : New Generations (ITNG 2008) (PDF) (BIB) |
Nader Bagherzadeh and Masaru Matsuura, "Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip," 5th International Conference on Information Technology : New Generations (ITNG 2008) (BIB) |
Jun Ho Bahn, Nader Bagherzadeh, "Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip(NoC) Architecture," 13th International CSI Computer Conference (CSICC 2008) (PDF) |
Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, and Nader Bagherzadeh, "A Generic Networ Interface Architecture for an NoC based Multiprocessor SoC," International Symposium on Architecture of Computing System(ARCS2008), Lecture Notes in Computer Science, vol.4934, pp.247-260, Feb.2008. (PDF) (BIB) |
Jun Ho Bahn, Seung Eun LEE, Yoon seok Yang, Jungsook Yang, and Nader Bagherzadeh, "Multi-Processor System Platform using Network-on-Chip (NoC) Techniques, " appears in Parallel Processing Letters. (PDF) (BIB) |
Jun-Ho Bahn, Seung Eun LEE, and Nader Bagherzadeh, "Design of a router for network-on-chip, " International Journal of High Performance Systems Architecture 2007 - Vol. 1, No.2 pp. 98 - 105. (PDF) |
Seung Eun Lee, Jun Ho Bahn and Nader Bagherzadeh, "Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)," Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), Oct. 2007 (PDF) (BIB) |
Akira Hatanaka , Nader Bagherzadeh, "A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template," Proceedings of the 21st International Parallel and Distributed Processing Symposium, IPDPS 2007. (PDF) |
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh, "Design and Analysis of a Feasible Network-on-Chip(NoC) Architecture," in the Proc. of ITNG 2007.(PDF) (BIB) |
Nozar Tabrizi, Nader Bagherzadeh, "A Parallel Sort Engine With Dynamic Memory For a Multiprocessor-on-a-Chip, " Proceedings of the Fourth IASTED International Conference, Circuits,Signals,and Systems ,Nov.2006 (PDF) |
Seung-Eun LEE, Nader Bagherzadeh, "Increasing the Throughput of an Adaptive Router in Network-on-Chip(NoC), " in the Proc. of 3rd Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2006. (PDF) |
Nozar Tabrizi, Nader Bagherzadeh, Amir H. Kamalizad and Haitao Du, "MaRS: A Macro-pipelined Reconfigurable System" in the Proc. of the 1st conference on Computing frontiers, 2004. (PDF) |
Invited Talks
"NePA: Multi-Processor System Platform Using a New Generation of Network-on-Chip Technique", IFIP WG 10.3 Workshop, June 2007. |
"Network-on-a-Chip (NoC): An Alternative Approach for the Design of Next Generation System-on-a-Chip (SoC)", High Performance Computing Group Seminar, HiPEAC Web Seminar, Apr. 2007 |
"Design and Analysis of an Network-on-Chip (NoC) processor Arichtecture", 4th International System-on-Chip (SoC) Conference & Exhibit, Nov. 2006, Newport Beach, CA |
Posters
Seung Eun LEE and Nader Bagherzadeh, "A Power-Aware Interconnection Network for a Multi-Processor SoC," in the Student Poster Session of the 6th Annual Industry Research Symposium, may. 2007 |
Seung-Eun LEE, Jun-Ho Bahn and Nader Bagherzadeh, "Design of An Adaptive Router Architecture for Network-on-Chip, " in the Student Poster Session of the 5th Annual Industry Research Symposium, May. 2006. (PDF) |
Patents
A Variable Frequency Link for an Interconnection Network, 2007, USA. Clock Boosting Mechanism for an Adaptive Wormhole Router, 2006, USA. |